| Operating Temperature: | 0~ 70(Celsius) |
|---|---|
| Technics: | Semiconductor IC |
| Power Supply Voltage (DC): | 3.30 V |
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CPLD adopts programming technologies such as CMOS EPROM, EEPROM, flash memory and SRAM to form a programmable logic device with high density, high speed and low power consumption. CPLD is mainly composed of three parts: logic block, programmable interconnect channel and I/O block. The logic block in CPLD is similar to a small-scale PLD, usually a logic block contains 4-20 macrocells, and each macrocell is generally composed of a product item array, a product item allocation, and a programmable register. Each macro unit has a variety of configuration methods, and each macro unit can also be used in cascade, so that more complex combinational logic and sequential logic functions can be realized. For CPLDs with a higher level of integration, an embedded array block with on-chip RAM/ROM is usually provided. Programmable interconnection channels mainly provide interconnection networks among logic blocks, macrocells, and input/output pins. The input/output block (I/O block) provides the interface between the internal logic and the device I/O pins. CPLDs with larger logic scales generally have built-in JTAG boundary scan test circuits, which can perform comprehensive system tests on programmed high-density programmable logic devices. In addition, in-system programming can also be carried out through the JTAG interface.
1.Pin Diagram:
2. MAX 7000B I/O Current During Power Sequencing:
Altera has identified that specific power sequence situations involving slow rise times on VCCIO or I/O pin voltage may cause MAX 7000B I/O pins to source/sink current before VCCINT is ramped. These conditions can violate the hot-socketing definition which indicates that these pins should be tri-stated during power-up and should not source/sink more than 300 μA of current per pin. There are two different power sequence situations where I/O pins may source or sink current greater than 300 μA.Table 2 describes the two power sequence issues and their possible workarounds.
3.I/O Transients During Fast Vccint Rise:
Altera has identified that fast VCCINT rise times can lead to pulses on I/O pins during the power-up period on MAX® 7000AE, MAX 3000A, and MAX 7000B devices. This condition can violate the hot-socketing definition that says these pins should be tri-stated during power-up and should not source or sink more than 300 μA of current per pin. There are two different pulses resulting from fast VCCINT rise times, a low pulse transient on any I/O pin, and a separate pulse transient on combinatorial output pins.Table 3 shows the issues and the MAX devices they affect.
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